GateMate™ FPGA

Power-Efficient FPGAs, Open-Source at Every Step

The GateMate™ FPGA family from Cologne Chip AG is tailored for small to medium-sized FPGA applications, offering exceptional logic density, power efficiency, compact packaging, and seamless PCB integration. With industry-leading cost efficiency, GateMate™ FPGAs are well-suited for everything from academic projects to high-volume production.

Thanks to their innovative architecture—combining CPE programmable elements with an intelligent routing engine—GateMate™ FPGAs enable flexible and efficient implementation of functions like scalable multipliers, unlocking new application possibilities through a superior circuit size-to-cost ratio.

Designs are synthesised with the open-source Yosys framework and supported by both Cologne Chip’s free P&R tool and a fully open-source flow using nextpnr with prjpeppercorn. Bitstreams can be loaded via flash, JTAG, or SPI using the open-source tool openFPGALoader.

Manufactured in Europe by Globalfoundries™ on a 28 nm Super Low Power (SLP) process, GateMate™ ensures supply chain reliability free from geopolitical risks and trade barriers.

GateMateTM FPGA Overview

The GateMate A1 FPGA is the most streamlined device in the GateMateTM Series. With its 20,480 logic elements, it is ideal for cost-sensitive and resource-efficient applications.

GateMate A1 Parameter
 Detail
Logic Cells 20,480 CPE correspond to
- 20,480 8-Input-LUT trees or
- 40,960 4-Input-LUT trees with
- 40,960 FFs/Latches
Block RAM Total 1,280 Kb
20Kb blocks: 64 or
40Kb blocks: 32
PLLs 4
SerDes 5 Gb/s 1
I/Os single-ended: 162
differential: 81
1.2V to 2.5V
double data rate (DDR) support
MIPI D-PHY comaptible
Performance Modes Low Power, Economy, Speed
(0.9V - 1.1V)
Temperature Range -40°C to +125°C
Package 324 balls 0.8mm fine pitch ball grid array (FBGA), 15x15 mm
GateMate-Overview

Novel CPE Architecture

  • 20,480 programmable elements (CPE) for combinatorial and sequential logic
  • 40,960 Latches / Flip-Flops within programmable elements
  • CPE consists of LUT-tree with 8 inputs
  • Each CPE configurable as 2-bit full-adder or 2x2-bit multiplier

Low Power Consumption

  • GlobalfoundriesTM 28 nm SLP (Super Low Power) process
  • 3 operation modes: low power, economy, speed
  • No excessive start-up currents
  • Only two supply voltages needed, can be applied in any order

Package

  • 324-ball BGA package (15x15 mm)
  • Only 2 signal layers required on PCB

Features

  • 4 programmable PLLs
  • Fast configuration with quad SPI interface up to 100 MHz
  • Multi-Chip configuration
  • 1,280 Kbit dual ported block RAM with variable data widths in 32 x 40 Kbit RAM cells
  • Multipliers with arbitrary size implementable in CPE array
  • Multiple clocking schemas
  • All 162 GPIOs configurable as single-ended or LVDS differential pairs
  • Double data rate (DDR) support in all GPIO cells
  • 5 Gb/s SerDes

GateMate-Features

Here you find all relevant documentation for GateMate™ FPGA. The files are organised by topic, providing quick access to the information you need. Should you have any questions, please do not hesitate to contact us.

Please note: Data is subject to change without notice. Some of the information provided may be protected by patents or other rights.

GateMate-Documentation

The GateMate™ FPGA Starter Kit offers an ideal entry point for embedded designers seeking a flexible, low-power platform based on the latest technology from Cologne Chip. It is designed for cost-sensitive projects and versatile applications.

  • Evaluation board featuring the GateMate A1 FPGA
  • Programmer adapter with a flat ribbon cable for custom PCBs
  • USB cable

This comprehensive kit provides the essential tools to kick-start your FPGA development.

GateMate-Developer

Leverage our fully open-source and constantly evolving toolchain ecosystem tailored for GateMate™ FPGAs and optimized for performance, flexibility and accessibility on all major platforms.

Download the Open-Source Toolchain ⬇

nextpnr running implementation with support for GateMate FPGA

Complete RTL-to-Bitstream Flow

GateMate™ FPGAs are supported by a streamlined open-source toolchain that includes:
Yosys

Supports Verilog, a load of SystemVerilog features, and VHDL via GHDL
nextpnr

Flexible place & route with GateMate support (prj-peppercorn)
openFPGALoader

Fast and versatile programmer with support for FTDI, RP2040, and various SPI flashes

Latest Builds

Get the latest builds directly from the official GitHub releases of the OSS CAD Suite:

🔗 Download Latest oss-cad-suite Builds (Windows, Linux, macOS, ARM)

These daily builds include all necessary tools (Yosys, nextpnr with GateMate support, openFPGALoader) pre-packaged for plug-and-play use.

💬 Need Help Getting Started?

Check out our Toolchain Installation Guide or reach out via Contact Us. Whether you’re on Windows, Linux, macOS or an ARM64 based Linux device — we’re here to help you get building in minutes.

🔍 Looking for the Legacy Toolchain?

🔗 Legacy Toolchain Packages for Windows (11.06.2025)
🔗 Legacy Toolchain Packages for Linux (11.06.2025)
Release Notes

Toolchain & Downloads

The Cologne Chip GateMateTM family addresses a complete range of system requirements. The following table compares all available devices:

A1 ✅A2 ✅A4 🔜A9A16A25
CPEs20,48040,96081,920184,320327,680512,000
Registers40,96081,920163,840368,640655,3601,024,000
Block RAM (20K/40K)64/32128/64256/128576/2881,024/5121,600/800
PLLs48163664100
SerDes12491625
Multipliersarbitraryarbitraryarbitraryarbitraryarbitraryarbitrary
Max. single-ended IOs162162154tbatbatba
Max. LVDS pairs818177tbatbatba
PackageFBGA324
15×15 mm		FBGA324
15×15 mm		FBGA324
15×15 mm		tbatbatba

✅ In mass production and available from stock in volumes

GateMate-Product-Table