GateMate™ FPGA

Ideal for Seamless Integration in Projects of Every Scale

The GateMate™ FPGA family from Cologne Chip AG is designed to meet the needs of small to medium-sized Field-programmable Gate Array applications. It offers best-in-class performance in terms of logic capacity, power efficiency, package size, and PCB compatibility. Additionally, GateMate™ FPGAs deliver the lowest cost in the industry, making them ideal for a wide range of uses, from university projects to high-volume production.

As a result of the outstanding circuit size/cost ratio, new applications can now leverage the benefits of FPGAs. This is made possible by an innovative FPGA architecture that integrates CPE programmable elements with a smart routing engine. The CPE architecture enables efficient construction of multipliers of any size. Memory-intensive applications can also benefit from block RAMs with bit widths ranging from 1 to 80 bits.

The General Purpose IOs (GPIOs) support voltage levels from 1.2 to 2.5 volts and can be configured as either single-ended or LVDS differential pairs. For high-speed communication, a SerDes interface is available.

FPGA designs are synthesised using the Yosys framework, while the free Cologne Chip P&R software generates the FPGA bitstream. The bitstream can be stored in external flash or configured directly via JTAG or SPI using the open-source programming tool openFPGALoader.

An integrated Static Timing Analysis (STA) tool highlights critical paths and assesses the overall design performance. Designers can also simulate their designs using Verilog netlist and SDF timing extraction.

Manufactured by Globalfoundries™ using their 28 nm Super Low Power (SLP) process, these devices are produced in Europe, ensuring a reliable supply chain that is free from risks associated with trade restrictions or excessive taxation.