GateMateTM FPGA
Empowering Innovation, Our FPGA Solution: Ideal for Seamless Integration in Projects of Every Scale, from small to High-Volume Applications.
The GateMateTM FPGA family of Cologne Chip AG addresses all application requirements of small to medium-sized FPGAs. Logic capacity, power consumption, package size, and PCB compatibility are best in class. Additionally, GateMateTM FPGAs combine these features with the lowest cost in the industry, making the devices well-suited for applications ranging from university projects to high-volume production. As a result of the outstanding circuit size/cost ratio, new applications can now leverage the benefits of FPGAs.
This is all based on a novel FPGA architecture, which combines CPE programmable elements with a smart routing engine. Specifically, the CPE architecture allows for the efficient construction of arbitrarily-sized multipliers. Furthermore, memory-aware applications can utilize block RAMs with bit widths of 1 to 80 bits.
General Purpose IOs (GPIOs) voltage levels range from 1.2 to 2.5 volts. Additionally, all GPIOs can be configured as single-ended or LVDS differential pairs. Furthermore, a high-speed SerDes interface is available.
Engineers synthesize FPGA designs using the Yosys framework. Moreover, the free Cologne Chip P&R software generates the FPGA bitstream. It can be stored in an external flash or configured directly via JTAG or SPI using the open programming tool openFPGALoader.
An integrated Static Timing Analysis (STA) provides evidence of critical paths and the overall performance of a design. Additionally, designers can simulate the design using Verilog netlist and SDF timing extraction.
GlobalfoundriesTM manufactures the devices using their 28 nm SLP (Super Low Power) process. Manufacturing in Europe ensures a reliable supply chain, free from the risks of trade restrictions or high taxation.
GateMateTM FPGA Overview
The GateMate A1 FPGA is the smallest-dimensioned component of the GateMateTM Series. With its 20,480 logic elements, it is ideally suited for lowest-power applications.
CCGM1A1 Parameter |
Detail |
Logic Cells | 20,480 CPE correspond to * 20,480 8-Input-LUT trees or * 40,960 4-Input-LUT trees with * 40,960 FF/Latches |
Block RAM | Total 1,280 Kb 20Kb blocks: 64 40Kb blocks: 32 |
PLLs | 4 |
SerDes 5 Gb/s | 1 |
I/Os | single-ended: 162 differential: 81 1.2V to 2.5V double data rate (DDR) support |
Performance Modes | Low Power, Economy, Speed (0.9V - 1.1V) |
Package | 324 balls 0.8mm fine pitch ball grid array (FBGA), 15x15 mm |
GateMateTM FPGA Features
Novel CPE Architecture
- 20,480 programmable elements (CPE) for combinatorial and sequential logic
- 40,960 Latches / Flip-Flops within programmable elements
- CPE consists of LUT-tree with 8 inputs
- Each CPE configurable as 2-bit full-adder or 2x2-bit multiplier
Low Power Consumption
- GlobalfoundriesTM 28 nm SLP (Super Low Power) process
- 3 operation modes: low power, economy, speed
- No excessive start-up currents
- Only two supply voltages needed, can be applied in any order
Features
- 4 programmable PLLs
- Fast configuration with quad SPI interface up to 100 MHz
- Multi-Chip configuration
- 1,280 Kbit dual ported block RAM with variable data widths in 32 x 40 Kbit RAM cells
- Multipliers with arbitrary size implementable in CPE array
- Multiple clocking schemas
- All 162 GPIOs configurable as single-ended or LVDS differential pairs
- Double data rate (DDR) support in all GPIO cells
- 5 Gb/s SerDes
Package
- 324-ball BGA package (15x15 mm)
- Only 2 signal layers required on PCB
Here you can find all relevant documentation for GateMateTM FPGA. Files are gouped by topic, so you will have quick access to the requested information. Please feel free to contact us for any questions.
Note: Data can change without notice. Parts of the information presented may be protected by patent or other rights.
Datasheets
- Technology Brief of GateMate FPGA Technology
- GateMate CCGM1A1/A2 Datasheet (May 2024)
- GateMate CCGM1A1/A2 Pin Lists (May 2024)
- GateMate Evaluation Board Datasheet (January 2024)
- GateMate Evaluation Board Version 3.1 Schematics (January 2024)
- GateMate Evaluation Board Version 3.2 Schematics (January 2024)
- GateMate Programmer Datasheet (August 2023)
- GateMate Programmer Version 1.3 Schematics (August 2023)
- GateMate Programmer Version 1.4 Schematics (August 2023)
User Guides
- GateMate Primitives Library (July 2024)
- GateMate Primitives Examples (May 2024)
- GateMate Toolchain Installation User Guide (August 2024)
Application Notes
Packaging Regulations and Declarations
- REACH Declaration for GateMate FPGA (2024)
- RoHS Declaration for GateMate FPGA (2023)
- Packaging Regulations and Soldering Reflow Information for GateMate FPGA
CAD Models
- KiCad Symbols and Footprint in kicad-symbols and kicad-footprints
- Altium Designer Symbols and Footprint
GateMateTM FPGA Starter Kit
The GateMateTM FPGA Starter Kit is the perfect starting point for all embedded designers exploring a flexible and low-power platform, based on the latest Cologne Chip technology and targeted at cost-sensitive designs.
The Starter Kit consists of all required hardware components for evaluating and developing a wide range of applications and includes:
- Evaluation Board with GateMate A1 FPGA
- Programmer Adapter and flat ribbon cable for your own PCB
- USB cable
GateMateTM FPGA Series: Feature Summary by Device
The Cologne Chip GateMateTM family addresses a complete range of system requirements. The following table compares all available devices:
Device | Rel. size | Programmable Elements (CPE) 1) 2) |
Block RAM 3) | PLLs | SerDes | I/Os | Package | ||||
CPEs | FF/Latches | 20Kb | 40Kb | single-ended | differential (LVDS) |
balls | size (mm) | ||||
CCGM1A1 | 1 | 20,480 | 40,960 | 64 | 32 | 4 | 1 | 162 | 81 | 324BGA | 15x15 |
CCGM1A2 | 2 | 40,960 | 81,920 | 128 | 64 | 8 | 2 | 162 | 81 | 324BGA | 15x15 |
CCGM1A4 | 4 | 81,920 | 163,840 | 256 | 128 | 16 | 4 | 154 | 77 | 324BGA | 15x15 |
CCGM1A9 | 9 | 184,320 | 368,640 | 576 | 288 | 36 | 9 | tba | tba | tba | tba |
CCGM1A16 | 16 | 327,680 | 655,360 | 1,024 | 512 | 64 | 16 | tba | tba | tba | tba |
CCGM1A25 | 25 | 512,000 | 1,024,000 | 1,600 | 800 | 100 | 25 | tba | tba | tba | tba |
1) CPEs have 2x4 or 8 inputs connected to a LUT tree 2) Each CPE can be used as 2x2 bit multiplier 3) Block RAM can have a max. data width of 20, 40 or 80 Bits