GateMate FPGA

The GateMate^TM FPGA family of Cologne Chip AG addresses all application requirements of small to medium-sized FPGAs. Logic capacity, power consumption, package size, and PCB compatibility are best in class. Additionally, GateMate^TM FPGAs combine these features with the lowest cost in the industry, making the devices well-suited for applications ranging from university projects to high-volume production. As a result of the outstanding circuit size/cost ratio, new applications can now leverage the benefits of FPGAs.

This is all based on a novel FPGA architecture, which combines CPE programmable elements with a smart routing engine. Specifically, the CPE architecture allows for the efficient construction of arbitrarily-sized multipliers. Furthermore, memory-aware applications can utilize block RAMs with bit widths of 1 to 80 bits.

General Purpose IOs (GPIOs) voltage levels range from 1.2 to 2.5 volts. Additionally, all GPIOs can be configured as single-ended or LVDS differential pairs. Furthermore, a high-speed SerDes interface is available.

Engineers synthesize FPGA designs using the Yosys framework. Moreover, the free Cologne Chip P&R software generates the FPGA bitstream. It can be stored in an external flash or configured directly via JTAG or SPI using the open programming tool openFPGALoader.

An integrated Static Timing Analysis (STA) provides evidence of critical paths and the overall performance of a design. Additionally, designers can simulate the design using Verilog netlist and SDF timing extraction.

GlobalfoundriesTM manufactures the devices using their 28 nm SLP (Super Low Power) process. Manufacturing in Europe ensures a reliable supply chain, free from the risks of trade restrictions or high taxation.