A new approach to PLL Technology
For general purpose Phase Locked Loops (PLLs), ASIC designers have to rely on analog VCOs until today. Now Cologne Chip has come up with a fully digital approach: C3-PLL-2, an IP core for frequency synthesizer applications.
A patent is pending for this innovation of Cologne Chip.
C3-PLL-2 relies on the DIGICC design concept of Cologne Chip. This makes it possible to easily implement the core in all process technologies: C3-PLL-2 is a fully digital circuitry using standard cell libraries. Because of its pure digital nature, the PLL does neither need any additional pad or pin nor external or internal loop capacitors. On top of that, normally no external filters for the supply voltage are required.
The lock time of the PLL is very short - it is even super-fast when the PLL is restarted after stand-by mode. Furthermore the silicon space used is smaller than that of competing technologies.
- Fully digital - designed for use with standard cell libraries for digital logic
- Implementable in any digital CMOS process technology
- Typical oscillator frequency ranges:
0.50 µm: 60-120 MHz
0.35 µm: 100-200 MHz
0.25 µm: 140-280 MHz
0.18 µm: 160-320 MHz
0.13 µm: 180-360 MHz
90 nm: 200-400 MHz
- Frequency multiplication range: 5 to 255
- Predivider and post-scaler with divider range 1..256 each
- Jitter similar to analog PLLs
- No pads, special pins, external loop filter capacity or supply voltage filters needed
- Very fast lock time (worst case 2,000 reference clocks)
- Stand-by mode (oscillator stopped but center frequency adjustments preserved)
DIGICC is a highly sophisticated new approach for ASIC projects, meeting mixed mode requirements with pure digital logic
The first Cologne Chip PLL core is based on the innovative DIGICC technology. Traditionally telecommunication ICs require analog cores making designs inflexible and expensive. New DIGICC-based C3-PLL-2 does offer fully digital implementations instead of these analog functional blocks