GateMate™ FPGA

Power-Efficient FPGAs, Open-Source at Every Step

The GateMate™ FPGA family from Cologne Chip AG is tailored for small to medium-sized FPGA applications, offering exceptional logic density, power efficiency, compact packaging, and seamless PCB integration. With industry-leading cost efficiency, GateMate™ FPGAs are well-suited for everything from academic projects to high-volume production.

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  • In mass production
  • Available from stock in volumes
Where to buy
Toolchain & Downloads
📄 GateMate A1/A2 Datasheet

GateMateTM FPGA Overview

 

The GateMate A1 FPGA is the most streamlined device in the GateMateTM Series. With its 20,480 logic elements, it is ideal for cost-sensitive and resource-efficient applications.

 

GateMate A1 Parameter
 Detail
Logic Cells 20,480 CPE correspond to
– 20,480 8-input LUT-trees or
– 40,960 4-input LUT-trees with
– 40,960 FFs/latches
Block RAM Total 1,280 Kb
20Kb blocks: 64 or
40Kb blocks: 32
PLLs 4
SerDes 5 Gb/s 1
I/Os single-ended: 162
differential: 81
1.2V to 2.5V
double data rate (DDR) support
MIPI D-PHY comaptible
Performance Modes Low Power, Economy, Speed
(0.9V – 1.1V)
Temperature Range -40°C to +125°C
Static Power 12 mA (1.0V core, 25°C)
Package 324 balls 0.8mm fine pitch ball grid array (FBGA), 15×15 mm
GateMate-Overview

Here you find all relevant documentation for GateMate™ FPGA. The files are organised by topic, providing quick access to the information you need. Should you have any questions, please do not hesitate to contact us.

Please note: Data is subject to change without notice. Some of the information provided may be protected by patents or other rights.

GateMate-Documentation

The GateMate™ FPGA Starter Kit offers an ideal entry point for embedded designers seeking a flexible, low-power platform based on the latest technology from Cologne Chip. It is designed for cost-sensitive projects and versatile applications.

  • Evaluation board featuring the GateMate A1 FPGA
  • Programmer adapter with a flat ribbon cable for custom PCBs
  • USB cable

This comprehensive kit provides the essential tools to kick-start your FPGA development.

GateMate-Developer

The fully open-source and license-free toolchain provides a complete flow for GateMate™ FPGAs — including synthesis, place & route, bitstream generation, and more.

Designed for usability and performance, the toolchain is lightweight, easy to install, and runs on all major platforms.

Download the Open-Source Toolchain ⬇

nextpnr running implementation with support for GateMate FPGA

Build times are remarkably faster compared to traditional vendor tools, and the open nature of the ecosystem offers transparency, customization, and integration with a broad range of open-source tools.

Complete RTL-to-Bitstream Flow

GateMate™ FPGAs are supported by a streamlined open-source toolchain that includes:

Latest Builds

Get the latest builds directly from the official GitHub releases of the OSS CAD Suite:

🔗 Download Latest oss-cad-suite Builds (Windows, Linux, macOS, ARM)

These daily builds include all necessary tools (Yosys, nextpnr with GateMate support, openFPGALoader) pre-packaged for plug-and-play use.

💬 Need Help Getting Started?

Feel free to reach out via Contact Us. Whether you’re on Windows, Linux, macOS or an ARM64 based Linux device — we’re here to help you get building in minutes.

How to use Yosys for Synthesis 

$ yosys
    -ql <logfile>
    -p '
        read_verilog -sv <sources>; # read verilog files with sv support
        synth_gatemate
            -top <topmodule>        # top module name
            -luttree                # mandatory: enable luttree support
            -nomx8                  # mandatory: disable MUX8 support
            -nomult;                # optional: disable hardware multipliers
        write_json <netlist>.json;  # write JSON netlist for implementation
        write_verilog <netlist>.v   # optional:write verilog netlist
    '
How to use nextpnr for Implementation 

$ nextpnr-himbaechel
    --device=CCGM1A1        # GateMate device, select CCGM1A1 or CCGM1A2
    --json <netlist>.json   # input netlist after `yosys`
    -o ccf=<file>.ccf       # input CCF pin constraints file
    -o out=impl.txt         # output textfile for bitstream generation
    --sdc <constraints>     # optional: input SDC constraints file
    --router router2        # router, always select `router2`
How to pack the Bitstream 

$ gmpack
    --spimode <mode>    # optional: flash spi mode to use (single, dual, quad)
    --crcmode <mode>    # optional: crc error behaviour (check, ignore, unused)
    --background        # optional: enables background reconfiguration in flash mode
    <input>.txt         # input textfile after `nextpnr`
    <output>.bit        # output bitfile for programmer
How to configure the FPGA via JTAG 

$ openFPGALoader
    --index-chain <no>  # optional: device index in JTAG chain
    --freq <freq>       # optional: programmer frequency in Hz (default 6M)
    -b <board>          # gatemate_evb_jtag: jtag, olimex_gatemateevb: dirtyJtag
    <bitfile>           # input bitfile after `gmpack`
How to configure the FPGA via SPI 

$ openFPGALoader
    --freq <freq>       # optional: programmer frequency in Hz (default 6M)
    -b <board>          # gatemate_evb_spi: spi
    -m                  # write bitstream in SRAM
    <bitfile>           # input bitfile after `gmpack`
How to store the Bitstream in external Flash 

$ openFPGALoader
    --index-chain <no>  # optional: device index in JTAG chain
    --freq <freq>       # optional: programmer frequency in Hz (default 6M)
    -b <board>          # gatemate_evb_jtag: jtag, gatemate_evb_spi: spi, olimex_gatemateevb: dirtyJtag
    -f                  # write bitstream in flash
    <bitfile>           # input bitfile after `gmpack`

🔍 Looking for the Legacy Toolchain?

🔗 Legacy Toolchain Packages for Windows (30.07.2025)
🔗 Legacy Toolchain Packages for Linux (30.07.2025)
Release Notes

Toolchain & Downloads

The Cologne Chip GateMateTM family addresses a complete range of system requirements. The following table compares all available devices:

A1 ✅A2 ✅A4 🔜A9A16A25
CPEs20,48040,96081,920184,320327,680512,000
Registers40,96081,920163,840368,640655,3601,024,000
Block RAM (20K/40K)64/32128/64256/128576/2881,024/5121,600/800
PLLs48163664100
SerDes12491625
Multipliersarbitraryarbitraryarbitraryarbitraryarbitraryarbitrary
Max. single-ended IOs162162154tbatbatba
Max. LVDS pairs818177tbatbatba
PackageFBGA324
15×15 mm		FBGA324
15×15 mm		FBGA324
15×15 mm		tbatbatba

✅ In mass production and available from stock in volumes

GateMate-Product-Table

28nm – Made in Germany

Manufactured using Globalfoundries advanced 28nm Super Low Power (SLP) process technology, GateMate FPGAs deliver good performance and energy efficiency. Produced in Germany, they ensure best quality and a robust supply chain at all times.

Innovative FPGA Architecture

GateMate’s architecture is built around an efficient 8-input LUT-tree, enabling complex logic functions with minimal resource usage. Integrated scalable multipliers and 8-input multiplexers provide enhanced arithmetic capabilities and flexible data routing.

Innovative Multi-Die Concept

Cologne Chip’s patented in-silicon die-to-die interconnects allow larger FPGAs to be cut from a single wafer and enables considerably more and faster connections between multiple dies in one package.

Instant-on Configuration

Experience near-instant FPGA readiness with GateMate’s ultra-fast configuration capabilities. Support for 100 MHz Quad-IO SPI, JTAG and a customizable internal interface ensures seamless integration and the flexibility to build proprietary configuration systems.

Flexible Multipliers

Each logic cell features a compact 2×2 bit multiplier with direct interconnection to neighboring cells: This architecture enables arbitrary-sized multipliers at any position on the chip, optimizing designs for DSP and filter applications.

Easy Integration and Pin Compatibility

GateMate’s smallest BGA package with up to 9 GPIO banks simplifies PCB design with easy escape routability on just 2 signal layers. Pin compatibility across GateMate A1, A2 and A4 ensures seamless upgrades and design flexibility.

High-speed Serial Interface

The GateMate SerDes achieves line rates up to 5 Gbit/s. It features highly-configurable data paths (16/20-, 32/40- or 64/80-bit), 8B/10B encoding/decoding, automatic comma detection, RX clock data recover, TX emphasis control mechanisms and various tools for assessing the signal integrity in your environment.

Wide Temperature Range

GateMate FPGAs operate reliably across an extended temperature range from -40 °C to +125 °C. This makes them ideal for industrial, automotive, and other mission-critical applications requiring high thermal resilience.

Bitstream Scrubber

This built-in mechanism, that continuously refreshes the configuration bits, enhances reliability and fault tolerance, making the devices well-suited for radiation-prone environments such as aerospace, medical, or high-altitude applications.

Open Toolchain and Ecosystem

GateMate FPGAs embrace open source innovation with support for powerful tools like Yosys for synthesis, nextpnr for place & route and openFPGALoader for programming. Additionaly, they integrate seamlessly into the LiteX SoC builder framework, enabling developers to leverage a rich ecosystem for efficient and flexible FPGA design.

 

 
 

Discover GateMate FPGA now!