Cologne Chip GateMate FPGA Tools
Release Notes

Last updated: 2024-10-24

## 2024-10.002
 * Added C_L simulation model to 'cpelib.v'.
 * Pass all CC_PLL parameters to post-implementation netlist.
 * Fixed CC_FIFO configuration for almost full/empty detection

## 2024-10.001
 * Improved verilog netlist parsing.
 * Improved error handling for false, incomplete or missing CCF files.
 * Vebose multiplier warnings.
 * Fixed multiplier input assignments.
 * Fixed ODDR clock inversion.
 * Intelligent handling for partially connected IOBUFs.
 * Allow integer type reference and output clock parameters for PLL.

## 2024-07.002
 * Improved warnings for combinatorial loops.
 * Allow 'NET' keyword in CCF for automatic buffer direction determination.
 * Improved CC_PLL simulation model.
 * Improved netlist vector parsing.

## 2024-05.002
 * Initial GateMate A2 and A4 support.
 * Enhanced power reduction through CP-line deactivation.
 * Less cumbersome import of delay files using p_r's path variable.
 * Fixed configruation with IOSEL/ODDR and tri-state IO buffers.
 * Improved verilog frontend for parsing post-synthesis netlists.
 * Updated openFPGALoader to v0.12.1.

## 2024-02.001
 * RAM pre-placement support using loc parameter.
 * Merge ADDF2/D to save CPE resources.
 * Improved SDF generator for timing simulation with modelsim and questasim.
 * Improved cpelib.
 * Improved openFPGALoader support for JTAG chains.
 * Updated delay files.

## 2023-10.003
 * Automatic BUFG mapping based on fanout, if more than 4 BUFG in netlist.
 * Symmetric placer improvements.
 * SerDes: Added the full set of primitive parameters.
 * Fixed IOSEL clock inversion.
 * Fixed block RAM configuration.
 * Updated delay files.

## 2023-08.001
 * Fixed DS4 to ICOMP mapping.
 * Enable SERDES_CFG_EN bit during configuration for regfile access from CPE.
 * Fixed missing C_PXin RTL_I bit for CPE multipliers.

## 2023-07.002
 * Verilog generator: Fixed output of similar signal and bus names.

## 2023-07.001
 * Fixed LVDS buffer parameter parsing.
 * Maintain capitalization in module names.
 * Fixed specific inverter in CPE configuration.
 * Added prioritized Block RAM placement to prevent IO congestions.
 * Updated delay files.

## 2023-06.001
 * Fixed parsing of 'UNDEFINED' pin names.
 * Prevent implicit declarations in cpelib.

## 2023-05.001
 * Add support for the CC_FIFO_40K primitive.
 * Improved Block RAM placement.
 * Fixed Block RAM / GPIO congestions.
 * Updated delay files.

## 2023-04.003
 * Fixed verilog parser to interpret ":" in signal names.
 * Revised Block RAM counter for utiliziation report.
 * Updated delay files.

## 2023-02.001
 * Add support for register initialization during configuration.
 * Improved utilitation reports.