Toolchain & Downloads

The fully open-source and license-free toolchain provides a complete flow for GateMate™ FPGAs — including synthesis, place & route, bitstream generation, and more.

Designed for usability and performance, the toolchain is lightweight, easy to install, and runs on all major platforms.

Download the Open-Source Toolchain ⬇

nextpnr running implementation with support for GateMate FPGA

Build times are remarkably faster compared to traditional vendor tools, and the open nature of the ecosystem offers transparency, customization, and integration with a broad range of open-source tools.

Complete RTL-to-Bitstream Flow

GateMate™ FPGAs are supported by a streamlined open-source toolchain that includes:

Latest Builds

Get the latest builds directly from the official GitHub releases of the OSS CAD Suite:

🔗 Download Latest oss-cad-suite Builds (Windows, Linux, macOS, ARM)

These daily builds include all necessary tools (Yosys, nextpnr with GateMate support, openFPGALoader) pre-packaged for plug-and-play use.

💬 Need Help Getting Started?

Feel free to reach out via Contact Us. Whether you’re on Windows, Linux, macOS or an ARM64 based Linux device — we’re here to help you get building in minutes.

How to use Yosys for Synthesis 

$ yosys
    -ql <logfile>
    -p '
        read_verilog -sv <sources>; # read verilog files with sv support
        synth_gatemate
            -top <topmodule>        # top module name
            -luttree                # mandatory: enable luttree support
            -nomx8                  # mandatory: disable MUX8 support
            -nomult;                # optional: disable hardware multipliers
        write_json <netlist>.json;  # write JSON netlist for implementation
        write_verilog <netlist>.v   # optional:write verilog netlist
    '
How to use nextpnr for Implementation 

$ nextpnr-himbaechel
    --device=CCGM1A1        # GateMate device, select CCGM1A1 or CCGM1A2
    --json <netlist>.json   # input netlist after `yosys`
    -o ccf=<file>.ccf       # input CCF pin constraints file
    -o out=impl.txt         # output textfile for bitstream generation
    --sdc <constraints>     # optional: input SDC constraints file
    --router router2        # router, always select `router2`
How to pack the Bitstream 

$ gmpack
    --spimode <mode>    # optional: flash spi mode to use (single, dual, quad)
    --crcmode <mode>    # optional: crc error behaviour (check, ignore, unused)
    --background        # optional: enables background reconfiguration in flash mode
    <input>.txt         # input textfile after `nextpnr`
    <output>.bit        # output bitfile for programmer
How to configure the FPGA via JTAG 

$ openFPGALoader
    --index-chain <no>  # optional: device index in JTAG chain
    --freq <freq>       # optional: programmer frequency in Hz (default 6M)
    -b <board>          # gatemate_evb_jtag: jtag, olimex_gatemateevb: dirtyJtag
    <bitfile>           # input bitfile after `gmpack`
How to configure the FPGA via SPI 

$ openFPGALoader
    --freq <freq>       # optional: programmer frequency in Hz (default 6M)
    -b <board>          # gatemate_evb_spi: spi
    -m                  # write bitstream in SRAM
    <bitfile>           # input bitfile after `gmpack`
How to store the Bitstream in external Flash 

$ openFPGALoader
    --index-chain <no>  # optional: device index in JTAG chain
    --freq <freq>       # optional: programmer frequency in Hz (default 6M)
    -b <board>          # gatemate_evb_jtag: jtag, gatemate_evb_spi: spi, olimex_gatemateevb: dirtyJtag
    -f                  # write bitstream in flash
    <bitfile>           # input bitfile after `gmpack`

🔍 Looking for the Legacy Toolchain?

🔗 Legacy Toolchain Packages for Windows (11.06.2025)
🔗 Legacy Toolchain Packages for Linux (11.06.2025)
Release Notes